The present invention relates to analog-to-digital converters, and, more specifically, to charge transfer analog-to-digital converters having means for precisely controlling the size of packets of charge transferred in the conversion process.
Charge transfer analog-to-digital converters (ADC s), as described, for example, in U.S. Pat. Nos. 4,065,766; 4,070,666; 4,070,667; 4,074,260; and 4,138,665, all assigned to the same assignee as the present application and incorporated herein by reference, provide ADCs suitable for implementation in monolithic integrated circuit form. The ADCs described in the aforementioned U.S. Patents provide numerous advantages over the prior art; however, sources of error, in the form of parasitic capacitances formed between the substrate and various electrodes of the elements of the monolithically integrated ADCs, exist. It is therefore desirable to provide an improved charge transfer analog-to-digital converter wherein such errors are minimized and, preferably, essentially removed.